Cyber Security Disruptions

Cyber security disruptions and how SPlunk is solving this using Machine learning, Data science to detect Cyber attacks.

Muddu Sudhakar is currently VP & GM Security & IOT, Splunk (www.splunk.com ). Before that Muddu was CEO of Caspida (www.caspida.com) and Caspida is leader in next-generation Cyber Security & Threat detection. Muddu Sudhakar is a seasoned and successful entrepreneur in the Silicon Valley. Muddu was VP & GM at VMware (www.vmware.com) and Pivotal (www.pivotal.io ) from 2012 to 2014 for Big Data Analytics and Cloud Services. At VMware & Pivotal Muddu had responsibility for wide range of projects Big Data Analytics, Cloud Services, Mobile Security. Muddu was co-founder and CEO of Cetas (www.cetas.net) which was acquired by VMware in 2012. At EMC (www.emc.com) Muddu was Chief Strategy Advisor, VP & GM for Cloud Information Services. Muddu work involved Cloud Infrastructure and Cloud Information Services at EMC. Muddu was CEO & Founder of Kazeon from 2003 to 2010 (www.kazeon.com) which was acquired by EMC(www.emc.com ) and Kazeon was leader in Enterprise Information Management, Information Security, eDiscovery, and Enterprise Search markets. Before Kazeon in 2003, he was Co-founder & President of Sanera Systems, a next-generation SAN technology company. Sanera was started in 1999 and was acquired by McData (Brocade) in 2003. From 1996 to 2000, Sudhakar was lead architect and designer of CPU and server technology at Silicon Graphics, Inc. Sudhakar holds a PhD and MS in Computer Science from University of California, Los Angeles and a BS in Electronics & Communications Engineering from Indian Institute of Technology, Madras. He is widely published in industry journals and conference proceedings and has more than 25 patents in Cyber Security, Big data analytics, Machine learning, Analytics, Data science, Cloud Services, Enterprise Search, Information Management, Distributed systems, Storage/Server technologies, Virtualization, Information security, Networking technology and VLSI chip design.